A basic TFET structure can be similar to a metal oxide semiconductor field effect transistor (MOSFET) structure except that the source and drain terminals of the TFET are doped of opposite type. That is, the TFET is an asymmetric device as compared to a symmetric MOSFET device. One conventional TFET device structure contains a P-I-N (p-type-intrinsic-n-type) junction, where the electrostatic potential of the intrinsic region is controlled by a gate terminal.
TFETs have the potential to serve as a viable option for extremely low power applications. However, unlike the conventional MOSFET in which the source and drain are symmetric, and can be readily formed to be self-aligned to the gate structure, due the TFET requirement to have different source and drain polarities it can be extremely challenging to form the different source and drain with a small gate length when using the conventional lithography. This is due at least to the presence of a reduced process window for mask placement with the small gate length. Another challenge relates to forming TFETs with a tight pitch (i.e., close spacing between TFETs).